Multi-stage charge pump with inter-stage limitation circuit

ABSTRACT

A multi-stage charge pump circuit including a first stage of the multi-stage charge pump having a first voltage output, a last stage of the multi-stage charge pump having a first voltage input, and an inter-stage limitation circuit configured to protect a voltage drop of the first voltage output of the first stage of the multi-stage charge pump when there is a voltage drop on the first voltage input of the last stage of the multi-stage charge pump.

TECHNICAL FIELD

Example embodiments disclosed herein relate generally to a multi-stagecharge pump circuit, and more particularly to a multi-stage charge pumpcircuit having an inter-stage current limitation circuit.

SUMMARY

A brief summary of various example embodiments is presented below. Somesimplifications and omissions may be made in the following summary,which is intended to highlight and introduce some aspects of the variousexample embodiments, but not to limit the scope of the invention.Detailed descriptions of example embodiments adequate to allow those ofordinary skill in the art to make and use the inventive concepts willfollow in later sections.

Example embodiments include a multi-stage charge pump circuit includinga first stage of the multi-stage charge pump having a first voltageoutput, a last stage of the multi-stage charge pump having a firstvoltage input, and an inter-stage limitation circuit configured toprotect a voltage drop of the first voltage output of the first stage ofthe multi-stage charge pump when there is a voltage drop on the firstvoltage input of the last stage of the multi-stage charge pump.

The first voltage output of the first stage of the multi-stage chargepump may connect to the first voltage input of the last stage of themulti-stage charge pump through the inter-stage limitation circuit.

The inter-stage limitation circuit may include a PMOS transistor inparallel with a large size resistor.

The PMOS transistor may be configured to be ON during a steady stateaction of the multi-stage charge pump.

The PMOS transistor may be configured to be OFF when the first voltageinput drops from a high state to a low state.

The inter-stage limitation circuit may include a first storage capacitorassociated with the first voltage output.

The inter-stage limitation circuit may include a second storagecapacitor associated with the first voltage input.

The first voltage output may be configured to provide power to othercircuits external to the multi-stage charge pump.

The inter-stage limitation circuit may include a small size resistor inseries with a large size resistor. The multi-stage charge pump circuitmay include an intermediary capacitor disposed between the small sizeresistor and the large size resistor.

Example embodiments also include an inter-stage limitation circuit,including a first capacitor to receive a charge from a first stage of amulti-stage charge pump, a small size resistor to pass a current storedin the first capacitor, a second capacitor to store a charge associatedwith a last stage of the multi-stage charge pump, an intermediatecapacitor to store an intermediate charge between the first capacitorand the second capacitor, a example embodiments large size resistor inseries with the small size resistor; and a PMOS transistor in parallelwith the large size resistor, wherein the PMOS transistor is in an OFFstate to enable the large size resistor and limit the current throughthe inter-stage limitation circuit.

The first capacitor, second capacitor, and intermediate capacitor may bearranged in parallel.

Example embodiments also include a method of operating a multi-stagecharge pump including ramping up a first voltage output of a first-stagecharge pump, ramping up a second voltage output of a last-stage chargepump in order to supply a voltage of an external switch, limiting acurrent draw on the first voltage output by enabling a high resistancebetween the first voltage output of the first-stage charge pump and afirst voltage input of the last-stage charge pump.

The method may include switching off a PMOS transistor that is inparallel with the high resistance to enable the high resistance betweenthe first stage and the last stage.

The method may include switching on a PMOS transistor that is inparallel with the high resistance to disable the high resistance betweenthe first stage and the last stage.

The first voltage output may be configured to provide power to othercircuits.

The method may include storing a first charge in a first capacitoradjacent an output of the first stage.

The method may include storing a second charge in an intermediatecapacitor between the first stage and the last stage.

The method may include storing a second charge in a second capacitoradjacent an input of the last stage.

The method may include storing and ramping up charge using a pluralityof capacitors arranged in parallel.

BRIEF DESCRIPTION OF THE DRAWINGS

Additional objects and features of the invention will be more readilyapparent from the following detailed description and appended claimswhen taken in conjunction with the drawings. Although several exampleembodiments are illustrated and described, like reference numeralsidentify like parts in each of the FIGURES, in which:

FIG. 1 illustrates a multi-stage charge pump 100 configured to power aswitch in accordance with example embodiments described herein.

DETAILED DESCRIPTION

It should be understood that the figures are merely schematic and arenot drawn to scale. It should also be understood that the same referencenumerals are used throughout the FIGURES to indicate the same or similarparts.

The descriptions and drawings illustrate the principles of variousexample embodiments. It will thus be appreciated that those skilled inthe art will be able to devise various arrangements that, although notexplicitly described or shown herein, embody the principles of theinvention and are included within its scope. Furthermore, all examplesrecited herein are principally intended expressly to be for pedagogicalpurposes to aid the reader in understanding the principles of theinvention and the concepts contributed by the inventor(s) to furtheringthe art and are to be construed as being without limitation to suchspecifically recited examples and conditions. Additionally, the term,“or,” as used herein, refers to a non-exclusive or (i.e., and/or),unless otherwise indicated (e.g., “or else” or “or in the alternative”).Also, the various example embodiments described herein are notnecessarily mutually exclusive, as some example embodiments can becombined with one or more other example embodiments to form new exampleembodiments. Descriptors such as “first,” “second,” “third,” etc., arenot meant to limit the order of elements discussed, are used todistinguish one element from the next, and are generallyinterchangeable. Values such as maximum or minimum may be predeterminedand set to different values based on the application.

As described herein, a plurality of charge pumps are included in amultiple stage charge pump and are connected in series, with the outputof one stage connected to the input of another stage. Depending upon adesired output voltage, a varied number of charge pumps stages may beused and enabled.

In a power delivery system or data communication system, multi-stagecharge pumps may be used, and charge pump outputs are shared to biasgate-source voltages of either power switches or data switches. Thepower or data switches may use NMOS transistors. These NMOS transistorswitches may be in an ON or OFF state independently of when themulti-stage charge pump is ON. Depending on the voltage levels of thedelivery power or the data signals passing through the NMOS switches,voltages from different charge pump stage outputs are applied to biasdifferent switches.

FIG. 1 illustrates a multi-stage charge pump 100 configured to power aswitch in accordance with example embodiments described herein. Themulti-stage charge pump 100 includes a first stage 110, a last stage 120and intermediate stages (not illustrated) between the first stage 110and the last stage 120. A supply voltage Vdd is applied to power thefirst stage 110 and the last stage 120. Enable signals 112 and 122 areused to select the first stage 110 and/or last stage 120 when outputvoltages are respectively requested therefrom. Output of the first stage110 of the multi-stage charge pump 100 may be designated Vcp1. Vcp1 maybe referred to as a first voltage output of the first stage 110 of themulti-stage charge pump 100. The first stage 110 and any intermediatestages contribute to the last stage to produce the multi-stage outputVcp_out. The output Vcp_out may be referred to as a second voltageoutput. The first stage 110 may also be designed as a LDO (low-drop-out)voltage regulator. The last stage 120 may also be designed as a LDO(low-drop-out) voltage regulator. The first stage 110, last stage 120,and intermediate stages (not illustrated) may also be designed as LDO(low-drop-out) voltage regulators.

The multi-stage charge pump 100 may conclude with a last stage 120. Anoutput from the last stage Vcp_out may be used to control a gate inputof a power switch 130. Example embodiments described herein may includea plurality of multi-stage charge pumps 100 to supply power to aplurality of power or data switches 130.

Inputs to the multi-stage charge pump 100 may include another supply orthe first stage 110 of the multi-stage charge pump 100. In order toreduce power consumption, the last stage 120 of the multi-stage chargepump 100 that is connected to the power switch 130 may be turned offwhile the first stage 110 is enabled. An output of the first stage maybe designated Vcp1 and stored in a first storage capacitor 162. Othercircuits 150 may be connected to and draw power from the first stage 110output Vcp1. The last stage 120 may have an input voltage Vcp3 thatconnects to the output voltage Vcp1. Vcp3 may be referred to as a firstvoltage input of the last stage 120 of the multi-stage charge pump 100.When Vcp_out is requested by the power switch 130, the voltage Vcp3 maydrop from a steady state high voltage to a lower voltage. In somedesigns of charge pumps without an inter-stage limitation circuit asdescribed herein, because the output Vcp1 of the first stage 110 is notan ideal power supply, transient current I1 is pulled from the firststorage capacitor 162 of the first stage 110 when the last stage 120 ofthe multi-stage charge pump 100 is enabled due to a large gate capacitorCgs of the power switch 130. The first stage 110 and second stage 120may be under the control of clock signals 114 and 124 that originatefrom a control circuit (not illustrated).

The transient current I1 is a function of the first stage 110 firststorage capacitor 162 and a capacitance Cgs of the power switch 130. Thecapacitance Cgs of the power switch 130 may be on the order of 1000 pF.The first stage 110 storage capacitor 162 may be on the order of 10 pFto 30 pF due to chip area sizing. Due to the large power switch 130 anda large Cgs of the power switch 130, the transient current I1 drawn fromthe output Vcp1 by the capacitance Cgs of the power switch 130 may belarge and cause a large voltage-drop on the first stage 110 output Vcp1.Without the use of an inter-stage current limitation circuit 140described herein, this large voltage drop may affect the function ofother circuits 150 that are connected to and drawing current from thefirst stage 110 output Vcp1.

According to example embodiments described herein, the inter-stagecurrent limitation circuit is applied between the first stage 110 andlast stage 120 of the multi-stage charge pump 100 to avoid the voltagedrop at Vcp1 without affecting a steady state function of the last stage120. The inter-stage current limitation circuit 140 allows an efficienttrade-off between the first stage voltage drop Vcp1 (by current limitingthe in-rush current) and start up time for the power switch 130.

In a case when the last-stage 120 is enabled after the first stage 110is enabled and the first stage 110 output voltage Vcp1 fully ramps up,during the ramping up of the last stage 120 output voltage Vcp_out,excess current I1 pulling from the first stage 110 due to the largepower switch 130 gate capacitance Cgs by the last stage 120 is limitedby the inter-stage current limitation circuit 140. Therefore, the firststage output Vcp1 may be protected and a large voltage drop on the firststage 110 is avoided.

As illustrated in FIG. 1, the first stage 110 of the multi-stage chargepump 100 may be configured to generate an output voltage Vcp1 accordingthe following equation when it is enabled and when its output voltagefully ramps up,

Vcp1=n*Vdd  (1)

where n is a natural number, and can be 2, or 3, or 4 depending on thedesign. Vdd is a chip power supply voltage (e.g., Vdd=3V, n=3, and Vcp1is about 9V). As discussed above, Vcp1 may be used as a voltage powersupply for other circuits 150, or bias data switches within the firststage 110 charge pump or LDO regulator.

The inter-stage current limitation circuit 140 is disposed between theoutput Vcp1 of the first stage 110 and the input Vcp3 of the last stage120. The last stage 120 generates an output voltage Vcp_out to bias agate source voltage Vgs of the power switch 130.

Without the inter-stage current limitation circuit 140, the voltage Vcp1is directly connected to the input Vcp3 of the last stage 120 of themulti-stage charge pump 100. The last stage 120 is enabled after thefirst stage 110 is enabled and Vcp1 fully ramps up. In this case, duringthe transient of ramping up of the last stage 120 to generate Vcp_out,the last stage 120 pulls excess current from Vcp1 to charge up thegate-source capacitance Cgs of the power switch 130. Therefore, Vcp3 andhence Vcp1 suffers from a large voltage drop to as low as 2V. Thisvoltage drop negatively affects the functionality of the othercircuit(s) 150 that Vcp1 is supplying.

To remedy this fluctuation, the inter-stage current limitation circuit140 includes components including the first storage capacitor 162, aseries resistor 152, an intermediary storage capacitor 164, a large sizeseries resistor 154, a PMOS transistor 170 in series with large sizeseries resistor 154, and a second storage capacitor 166. Theintermediary storage capacitor 164 may help store charge from the firststage output Vcp1. During the ramping up of Vcp_out, the capacitor 164may supply some of the charge. The series resistor may be on the orderof 10KΩ. The large series resistor may be on the order of 200KΩ. ThePMOS transistor 170 is in parallel arrangement with the large sizeseries resistor 154. Before Vcp_out ramps up, Vcp3 is high, and the PMOStransistor 170 is ON (because the voltage drop from drain to gate ishigh). The on resistance of the PMOS transistor 170 is small compared tothe large size series resistor 154, thus a high current draw is allowedbetween Vcp1 and Vcp3. During a transient time of Vcp_out ramping up, alarge voltage drop occurs at Vcp3. The voltage level at Vcp2 also drops.When Vcp2 drops to Vdc+abs(Vthp), the PMOS transistor 170 is switchedoff (because the voltage drop from drain to gate is low). Because thelarge size series resistor 154 is designed to be very large, the voltageVcp2 is clamped as indicated in the following equation

Vclamp(Vcp2)>Vdc+abs(Vthp)  (2)

where Vthp is the threshold voltage for the PMOS transistor 170 to beturned on, abs(Vthp) is an absolute value because Vthp is a negativevalue, and Vdc is pre-defined voltage, e.g.,

Vdc=(n−1)*Vdd  (3)

where Vdd is an input to the first stage 110. Vdc may be output from aprevious stage or may be an initial input from a power source.

As discussed, large size series resistor 154 is a very large resistanceto limit the current pulling from Vcp2 when the PMOS transistor 170 isoff to guarantee that Vcp2 is clamped. Series resistor 152 is a smallerresistance, together with the first storage capacitor 162 to furtherprotect Vcp1. In a steady state when Vcp_out fully ramps up, no excesscurrent is pulled from Vcp3. Vcp3 is charged up and the PMOS transistor170 is turned on. As noted above, the PMOS transistor 170 may have anon-resistance much smaller than large size series resistor 154, andtherefore, when the PMOS transistor 170 is turned on, large size seriesresistor 154 is by-passed, the resistance from the first stage 110 tothe last stage 120 is small, and the steady state function of themulti-stage charge pump 100 is not affected.

In other words, during the transient of Vcp_out ramping up, because thePMOS transistor 170 is off, the inter-stage current limitation circuit140 becomes a RC low pass filter with a very large RC time constant toprotect Vcp1 from the large voltage drop of Vcp3. In steady state, largesize series resistor 154 is by-passed by the PMOS transistor 170, andthe inter-stage current limitation circuit 140 becomes a RC low passfilter with very small RC time constant when protection is not needed.

As noted above regarding intermediate stage charge pumps, the firststage 110 may be designed as a single stage charge pump when n=2, ormulti-stage charge pump 100 when n>2. In another embodiment, the firststage 110 may be dispensed with, and Vcp1 may directly come from thepower supply Vdd.

Also the first stage 110 and the last stage 120 can be either anopen-loop or close-loop design with the voltage regulator. The voltageregulator may regulate the output voltage of each stage, or regulate agate-source voltage of switches each stage as biasing.

Example embodiments described herein may be applied to provide reliablefirst stage or intermediate stage charge pump output voltage and improvereliability of chip functionality.

Although the various example embodiments have been described in detailwith particular reference to certain exemplary aspects thereof, itshould be understood that the invention is capable of other exampleembodiments and its details are capable of modifications in variousobvious respects. As is readily apparent to those skilled in the art,variations and modifications can be affected while remaining within thespirit and scope of the invention. Accordingly, the foregoingdisclosure, description, and FIGURES are for illustrative purposes onlyand do not in any way limit the invention, which is defined only by theclaims.

1. A multi-stage charge pump circuit, comprising: a first stage of themulti-stage charge pump having a first voltage output; a last stage ofthe multi-stage charge pump having a first voltage input; and aninter-stage limitation circuit configured to protect a voltage drop ofthe first voltage output of the first stage of the multi-stage chargepump when there is a voltage drop on the first voltage input of the laststage of the multi-stage charge pump.
 2. The multi-stage charge pumpcircuit of claim 1, wherein the first voltage output of the first stageof the multi-stage charge pump connects to the first voltage input ofthe last stage of the multi-stage charge pump through the inter-stagelimitation circuit.
 3. The multi-stage charge pump circuit of claim 1,wherein the inter-stage limitation circuit includes a PMOS transistor inparallel with a large size resistor.
 4. The multi-stage charge pumpcircuit of claim 3, wherein the PMOS transistor is configured to be ONduring a steady state action of the multi-stage charge pump.
 5. Themulti-stage charge pump circuit of claim 3, wherein the PMOS transistoris configured to be OFF when the first voltage input drops from a highstate to a low state.
 6. The multi-stage charge pump circuit of claim 1,wherein the inter-stage limitation circuit includes a first storagecapacitor associated with the first voltage output.
 7. The multi-stagecharge pump circuit of claim 1, wherein the inter-stage limitationcircuit includes a second storage capacitor associated with the firstvoltage input.
 8. The multi-stage charge pump circuit of claim 1,wherein the first voltage output is configured to provide power to othercircuits external to the multi-stage charge pump.
 9. The multi-stagecharge pump circuit of claim 1, wherein the inter-stage limitationcircuit includes a small size resistor in series with a large sizeresistor.
 10. The multi-stage charge pump circuit of claim 9, comprisingan intermediary capacitor disposed between the small size resistor andthe large size resistor.
 11. An inter-stage limitation circuit,comprising: a first capacitor to receive a charge from a first stage ofa multi-stage charge pump; a small size resistor to pass a currentstored in the first capacitor; a second capacitor to store a chargeassociated with a last stage of the multi-stage charge pump; anintermediate capacitor to store an intermediate charge between the firstcapacitor and the second capacitor; a large size resistor in series withthe small size resistor; and a PMOS transistor in parallel with thelarge size resistor, wherein the PMOS transistor is in an OFF state toenable the large size resistor and limit the current through theinter-stage limitation circuit.
 12. The inter-stage limitation circuitof claim 11, wherein the first capacitor, second capacitor, andintermediate capacitor are arranged in parallel.
 13. A method ofoperating a multi-stage charge pump, comprising: ramping up a firstvoltage output of a first-stage charge pump; ramping up a second voltageoutput of a last-stage charge pump in order to supply a voltage of anexternal switch; limiting a current draw on the first voltage output byenabling a high resistance between the first voltage output of thefirst-stage charge pump and a first voltage input of the last-stagecharge pump.
 14. The method of claim 13, comprising switching off a PMOStransistor that is in parallel with the high resistance to enable thehigh resistance between the first stage and the last stage.
 15. Themethod of claim 13, comprising switching on a PMOS transistor that is inparallel with the high resistance to disable the high resistance betweenthe first stage and the last stage.
 16. The method of claim 13, whereinthe first voltage output is configured to provide power to othercircuits.
 17. The method of claim 13, comprising storing a first chargein a first capacitor adjacent an output of the first stage.
 18. Themethod of claim 13, comprising storing a second charge in anintermediate capacitor between the first stage and the last stage. 19.The method of claim 13, comprising storing a second charge in a secondcapacitor adjacent an input of the last stage.
 20. The method of claim13, comprising storing and ramping up charge using a plurality ofcapacitors arranged in parallel.